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| CCD Delay Line Series MN3867S PAL-Compatible CCD Video Signal Delay Element Overview The MN3867S is a CCD signal delay element for video signal processing applications. It contains such components as a threefold-frequency circuit, a shift register clock driver, charge I/O blocks, two CCD analog shift registers switchable between 1700 and 617 stages and between 848.5 and 617 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits. When the switch input is "L" level, the MN38667S samples the input using the supplied clock signal with a frequency three times the PAL color signal subcarrier frequency (4.43361875 MHz) and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) and 2 H for the two lines. When the switch input is "H" level, the MN38667S disables the threefold-frequency circuit and samples the input with the image sensor drive frequency (9.65625 MHz) for the camera's 510 horizontal pixels and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. Pin Assignment XIC VSS3 VDD3 VINC1 N.C. VINVC VGC1 VO1C VDD1 VSS1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 XIV PCOUT & VCOIN -VBB VSS2 VDD2 VINVY SW VINC2 VGC2 VO2Y ( TOP VIEW ) SOP020-P-0300C Features Single 5.0 V power supply Choice of camera and VCR modes, so that both the camera and VCR portions of a video camera with 510 horizontal pixels can use the same MN38667S for signal processing Applications Video cameras 1 MN3867S Block Diagram CCD Delay Line Series VGC1 16 V DD2 17 V SS2 10 14 Bias circuit Clamp circuit Mode switch Booster circuit Voltage generator VINVC 6 L H Charge input block Charge input block 1086-stage analog shift register L H 614-stage analog shift register L H Charge detector Voltage generator 8 VINC1 4 H L 3-stage analog shift register Resampling output amplifier 12 VO1C 11 VO2Y oS driver oR driver oSH driver oSH driver -VBB 18 3 2 9 VINVY 15 L H L Charge input block Charge input block 234.5-stage analog shift register H 614-stage analog shift register L H Charge detector Resampling output amplifier VINC2 13 H L XIV 20 L H 3-stage analog shift register H XIC 1 Waveform amplifier adjustment block 1/3rd frequency divider L Waveform adjustment block o1 driver L H VCO Timing adjustment L H o2 driver Phase comparator 19 2 PCOUT & VCOIN 7 Substrate bias generator VGC2 VDD1 VDD3 VSS1 VSS3 SW CCD Delay Line Series Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Notes 1: Always connect VDD1, VDD2, and VDD3 to the same voltage. 2: Always connect VSS1, VSS2, and VSS3 to ground. MN3867S Symbol XIC VSS3 VDD3 VINC1 N.C. VINVC VGC1 VO1C VDD1 VSS1 VO2Y VGC2 VINC2 SW VINVY VDD2 VSS2 -VBB PCOUT&VCOIN XIV Pin Name 9.65625 MHz clock input GND (3) Power supply (3) Camera signal input (1) No connection Video signal input (C) Output gate connection (1) Signal output (1C) Power supply (1) GND (1) Signal output (2Y) Output gate connection (2) Camera signal input (2) Camera/video mode switch Video signal input (Y) Power supply (2) GND (2) Substrate connection Phase comparator output and voltage controlled oscillator input 4.43361875 MHz clock input Remarks Ground for clock multiplier circuit Power supply for clock multiplier circuit Output pin for signal fed to pin 4 or pin 6 Power supply for analog circuits Ground for analog circuits Output pin for signal fed to pin 13 or pin 15 Power supply for digital circuits other than frequency multiplier Ground for digital circuits other than frequency multiplier Negative voltage pin 3 MN3867S Application Circuit Example CCD Delay Line Series + 5.0V - 10F 5.0V or GND 0.01F 0.01F 0.1F VGC1 Bias circuit Clamp circuit Mode switch Booster circuit Voltage generator Signal input VINVC 6 -+ 0.47F Signal input VINC1 4 -+ 0.47F Signal input VINVY 15 -+ 0.47F Signal input VINC2 13 -+ 0.47F Clock input XIV 20 1000pF Clock input XIC 1000pF L H H L Charge input block Charge input block 1086-stage analog shift register L H 614-stage analog shift register L H L Charge detector Voltage generator 8 VO1C Signal output (1C) 3-stage analog shift register 234.5-stage analog shift register Resampling output amplifier L H H L L H Charge input block Charge input block H 614-stage analog shift register Charge detector Resampling output amplifier 12 VGC2 11 VO2Y Signal output (2Y) oS driver oR driver oSH driver oSH driver 0.1F 0.1F VDD1 16 VDD2 10 VSS1 17 VSS2 VDD3 VSS3 14 SW 3 2 9 3-stage analog shift register H L H 1 Waveform amplifier adjustment block 1/3rd frequency divider L Waveform adjustment block o1 driver L H VCO Timing adjustment L H o2 driver Phase comparator 19 7 Substrate bias generator PCOUT & VCOIN -VBB 18 0.01F 1000pF 0.01F 820 Note: If the capacitor attached to pin 18 has a polarity, attach the negative pole to pin 18. 4 CCD Delay Line Series Package Dimensions (Unit:mm) SOP020-P-0300C MN3867S 12.630.3 20 11 5.50.3 7.60.3 0.2 -0.05 +0.10 0 to 10 1 10 2.050.2 (0.4) (0.6) 0.10 1.27 0.40.25 SEATING PLANE 0.10.1 5 |
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